In the usual prior art implementation of a clocked latching comparator, a clock signal switches the comparator between a sample mode and a latching mode. In the sample mode, the comparator has relatively low gain and the output follows the signal input. When the comparator is clocked into the latching mode, positive feedback is enabled so that an arbitrary small signal will regenerate and drive the latch to its full output swing, such that the signal is correctly resolved by subsequent logic.
FIG. 1 and FIG. 2 show a comparator circuit proposed by Albert E. Cosand (U.S. Pat. No. 6,597,303), utilizing transistors and resistors for regeneration. Although it is desirable to provide faster regeneration, the regeneration time of the comparator circuit of FIG. 1 and FIG. 2 is limited by an RC time constant determined by the resistance (R, including resistors and parasitic resistance) and the parasitic capacitance of the transistors (C). The value of the RC time constant in seconds is equal to the product of the circuit resistance in ohms and the circuit capacitance in farads, expressed mathematically as t=RC.